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? semiconductor components industries, llc, 2004 november, 2004 ? rev. 4 1 publication order number: ncp5220/d ncp5220 3?in?1 pwm dual buck and linear power controller the ncp5220 3?in?1 pwm a dual buck and linear power controller, is a complete power solution for mch and ddr memory. this ic combines the efficiency of pwm controllers for the vddq supply and the mch core supply voltage with the simplicity of linear regulator for the vtt termination voltage. this ic contains two synchronous pwm buck controller for driving four external n?ch fets to form the ddr memory supply voltage (vddq) and the mch regulator. the ddr memory termination regulator (vtt) is designed to track at the half of reference voltage with sourcing and sinking current. protective features include, soft?start circuitry, undervoltage monitoring of 5vdual, boot voltage and thermal shutdown. the device is housed in a thermal enhanced space?saving dfn?20 package. features ? pb?free package is available* ? incorporates synchronous pwm buck controllers for vddq and vmch ? integrated power fets with vtt regulator source/sink up to 2.0 a ? all external power mosfet s are n?channel ? adjustable vddq and vmch by external dividers ? vtt tracks at half the reference voltage ? fixed switching frequency of 250 khz for vddq and vmch ? doubled switching frequency of 500 khz for vddq controller in standby mode to optimize inductor current ripple and efficiency ? soft?start protection for all controllers ? undervoltage monitor of supply voltages ? overcurrent protections for ddq and vtt regulators ? fully complies with acpi power sequencing specifications ? short circuit protection prevents damage to power supply due to reverse dimm insertion ? thermal shutdown ? 5x6 dfn?20 package typical applications ? ddr i and ddr ii memory and mch power supply *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. pin connections device package shipping ? ordering information ncp5220mnr2 dfn?20 2500 tape & ree l ncp5220 = specific device code a = assembly location wl = wafer lot yy = year ww = work week marking diagram comp ss sw_ddq fbddq pgnd boot vtt 5vdual vddq agnd fbvtt slp_s5 fb1p5 bg_ddq tg_ddq comp_1p 5 slp_s3 tg_1p5 bg_1p5 gnd_1p5 dfn?20 mn suffix case 505ab 1 20 ncp5220 awlyyww 1 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. note: pin 21 is the thermal pad on the bottom of the device. ncp5220mnr2g dfn?20 (pb?free) 2500 tape & ree l http://onsemi.com
ncp5220 http://onsemi.com 2 fbvtt cout2 1.25 v, 2.0 apk ss css 1.5 v, 10 a tg_1p5 bg_1p5 pgnd m4 vmch 13 v zener m1 tg_ddq m2 sw_ddq bg_ddq rz2 r1 r2 fbddq comp cp1 rz1 cz1 vddq cout1 vddq 2.5 v, 20 a pgnd cz2 boot 12 v 5vdual l l cout3 rzm2 czm2 r5 r6 cpm1 rzm1 czm1 m3 5vdual fb1p5 comp_1p5 agnd figure 1. application diagram 5vdual vtt vtt ncp5220 slp_s5 slp_s5 slp_s3 slp_s3
ncp5220 http://onsemi.com 3 gnd_1p5 vddq + ilim l osc control logic tg_ddq pgnd sw_ddq bg_ddq voltage and current reference vref _vrefgd s0 s3 boot_ uvlo vref r10 r11 vcc thermal shutdown tsd 5vdual_ uvlo r12 r13 5vdual vref _5vdlgd _bootgd s0 s3 cout1 vddq comp rz2 cp1 rz1 cz1 fbddq r1 r2 amp a1 vref pgnd m1 css m2 m3 regulation control agnd vddq fbvtt r18 r19 r17 r16 agnd s0 5vdual 5vdual agnd pgnd cout2 5vdual 12 v boot 13 v zener amp_mch a1 vref pgnd pgnd m2 m4 m3 5vdual l2 cout3 vmch tp_1p5 bg_1p5 5vdual 5vdual and v1p5 pwm logic figure 2. internal block diagram ? + 180 phase shift vtt vcc vcc vcc v cc vtt slp_s3 slp_s5 ss vocp cz2 pgnd vcc comp_1p5 rzm2 cpm1 rzm1 czm1 fb1p5 rm1 rm2 czm2 vtt
ncp5220 http://onsemi.com 4 pin description pin symbol description 1 comp vddq error amplifier compensation node. 2 fbddq ddq regulator feedback pin. 3 ss soft?start pin of ddq and mch. 4 pgnd power ground. 5 vtt vtt regulator output. 6 vddq power input for vtt linear regulator. 7 agnd analog ground connection and remote ground sense. 8 fbvtt vtt regulator pin for closed loop regulation. 9 slp_s5 active low control signal to activate s5 power off state. 10 fb1p5 v1p5 switching regulator feedback pin. 11 gnd_1p5 power ground for v1p5 regulator. 12 bg_1p5 gate driver output for v1p5 regulator low side n?channel power fet. 13 tg_1p5 gate driver output for v1p5 regulator high side n?channel power fet. 14 slp_s3 active low control signal to activate s3 sleep state. 15 comp_1p5 v1p5 error amplifier compensation node. 16 5vdual 5.0 v dual supply input, which is monitored by undervoltage lock out circuitry. 17 boot gate driver input supply, which is monitored by undervoltage lock out circuitry, and a boost capacitor connection between swddq and this pin. 18 tg_ddq gate driver output for ddq regulator high side n?channel power fet. 19 bg_ddq gate driver output for ddq regulator low side n?channel power fet. 20 sw_ddq ddq regulator switch node and current limit sense input. 21 th_pad copper pad on bottom of ic used for heatsinking. this pin should be connected to the ground plane under the ic. maximum ratings rating symbol value unit power supply voltage (pin 16) to agnd (pin 7) 5vdual ?0.3, 6.0 v boot (pin 17) to agnd (pin 7) boot ?0.3, 14 v gate drive (pins 12, 13, 18, 19) to agnd (pin 7) vg ?0.3 dc, ?4.0 for 100 ns; 14 v input / output pins to agnd (pin 7) pins 1?3, 5, 6, 8?10, 14?15, 20 v io ?0.3, 6.0 v pgnd (pin 4), gnd_1p5 (pin 11) to agnd (pin 7) v gnd ?0.3, 0.3 v thermal characteristics dfn?20 plastic package thermal resistance junction?to?air r ja 35 c/w operating junction temperature range t j 0 to + 150 c operating ambient temperature range t a 0 to + 70 c storage temperature range t stg ? 55 to +150 c moisture sensitivity level msl 2.0 maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. this device series contains esd protection and exceeds the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22?a114. machine model (mm) 200 v per jedec standard: jesd22?a115. 2. latchup current maximum rating: 150 ma per jedec standard: jesd78.
ncp5220 http://onsemi.com 5 electrical characteristics (5vdual = 5.0 v, boot = 12 v, t a = 0 c to 70 c, l = 1.7 h, cout1 = 3770 f, cout2 = 470 f, cout3 = na, css = 33 nf, r1 = 2.166 k , r2 = 2.0 k , rz1 = 20 k , rz2 = 8.0 , cp1 = 10 nf, cz1 = 6.8 nf, cz2 = 100 nf, rm1 = 2.166 k , rm2 = 2.0 k , rzm1 = 20 k , rzm2 = 8.0 , cpm1 = 10 nf, czm1 = 6.8 nf, czm2 = 100 nf for min/max values unless otherwise noted). duplicate component values of mch regulator from ddq. characteristic symbol test conditions min typ max unit supply voltage 5vdual operating voltage v5vdual 4.5 5.0 5.5 v boot operating voltage vboot 12.0 13.2 v supply current s0 mode supply current from 5vdual i5vdl_s0 slp_s5 = high, slp_s3 = high, boot = 12 v, tg_1p5 and bg_1p5 open 10 ma s3 mode supply current from 5vdual i5vdl_s3 slp_s5 = high, slp_s3 = low, tg_1p5 and bg_1p5 open 5.0 ma s5 mode supply current from 5vdual i5vdl_s5 slp_s5 = low, boot = 0 v, tg_1p5 and bg_1p5 open 1.0 ma s0 mode supply current from boot iboot_s0 slp_s5 = high, slp_s3 = high, boot = 12 v, tg_1p5 and bg_1p5 open 25 ma s3 mode supply current from boot iboot_s3 slp_s5 = high, slp_s3 = low, tg_1p5 and bg_1p5 open 25 ma undervoltage?monitor 5vdual uvlo upper threshold v5vdluv+ 4.4 v 5vdual uvlo hysteresis v5vdlhys 250 400 550 mv boot uvlo upper threshold vbootuv+ 10.4 v boot uvlo hysteresis vboothys 1.0 v thermal shutdown thermal shutdown ts d (note 3) 145 c thermal shutdown hysteresis tsdhys (note 3) 25 c ddq switching regulator fbddq feedback voltage, control loop in regulation vfbq t a = 25 c t a = 0 c to 70 c 1.178 1.166 1.190 1.202 1.214 v feedback input current iddqfb v(fbddq) = 1.3 v 1.0 a oscillator frequency in s0 mode fddqs0 217 250 283 khz oscillator frequency in s3 mode fddqs3 434 500 566 khz oscillator ramp amplitude dvosc (note 3) 1.3 vp?p current limit blanking time in s0 mode tddqbk (note 3) 400 ns current limit threshold offset from 5vdual vocp (note 3) 0.8 v minimum duty cycle dmin 0 % maximum duty cycle dmax 100 % soft?start pin current for ddq iss1 v(ss) = 0.5 v 4.0 a ddq error amplifier dc gain gainddq (note 3) 70 db gain?bandwidth product gbwddq comp pin to gnd = 220 nf, 1.0 in series (note 3) 12 mhz slew rate srddq comp pin to gnd = 10 pf 8.0 v/us 3. guaranteed by design, not tested in production.
ncp5220 http://onsemi.com 6 electrical characteristics (5vdual = 5.0 v, boot = 12 v, t a = 0 c to 70 c, l = 1.7 h, cout1 = 3770 f, cout2 = 470 f, cout3 = na, css = 33 nf, r1 = 2.166 k , r2 = 2.0 k , rz1 = 20 k , rz2 = 8.0 , cp1 = 10 nf, cz1 = 6.8 nf, cz2 = 100 nf, rm1 = 2.166 k , rm2 = 2.0 k , rzm1 = 20 k , rzm2 = 8.0 , cpm1 = 10 nf, czm1 = 6.8 nf, czm2 = 100 nf for min/max values unless otherwise noted). duplicate component values of mch regulator from ddq. characteristic unit max typ min test conditions symbol vtt active termination regulator vtt tracking ddq_ref/2 at s0 mode dvtts0 iout= 0 to 2.0 a (sink current) iout= 0 to ?2.0 a (source current) ?30 30 mv vtt source current limit ilimvtsrc 2.0 a vtt sink current limit ilimvtsnk 2.0 a control section slp_s5 , slp_s3 input logic high logic_h 2.0 v slp_s5 , slp_s3 input logic low logic_l 0.8 v slp_s5 , slp_s3 input current ilogic 1.0 a gate drivers tgddq gate pull?high resistance rh_tg vcc = 12 v, v(tgddq) = 11.9 v 3.0 tgddq gate pull?low resistance rl_tg vcc = 12 v, v(tgddq) = 0.1 v 2.5 bgddq gate pull?high resistance rh_bg vcc = 12 v, v(bgddq) = 11.9 v 3.0 bgddq gate pull?low resistance rl_bg vcc = 12 v, v(bgddq) = 0.1 v 1.3 tg1p5 gate pull?high resistance rh_tpg vcc = 12 v, v(tg1p5) = 11.9 v 3.0 tg1p5 gate pull?low resistance rl_tpg vcc = 12 v, v(tg1p5) = 0.1 v 2.5 bg1p5 gate pull?high resistance rh_bpg vcc = 12 v, v(bg1p5) = 11.9 v 3.0 bg1p5 gate pull?low resistance rl_bpg vcc = 12 v, v(bg1p5) = 0.1 v 1.3 mch switching regulator vfb1p5 feedback voltage, control loo in regulation vfb1p5 t a = 0 c to 70 c 0.784 0.8 0.816 v feedback input current i1p5fb 1.0 a oscillator frequency f1p5 217 250 283 khz oscillator ramp amplitude dv1p5osc (note 4) 1.3 vp?p minimum duty cycle dmin_1p5 0 % maximum duty cycle dmax_1p5 100 % soft?start pin current for v1p5 regulator iss2 (note 4) 8.0 a 4. guaranteed by design, not tested in production.
ncp5220 http://onsemi.com 7 typical operating characteristics ivtt, output load current (a) vtt, output voltage (vddq/2 v) sourcing/sinking current with 10 ms period and 1.0 ms pulse width t a = 25 c 0 20406080 t a , ambient temperature ( c) switching frequency (khz) 29.8 30 30.2 30.4 30.6 30.8 31 31.2 0 20406080 t a , ambient temperature ( c) vtt, sink current load regulation (mvp?p) 1.187 1.188 1.189 1.190 1.191 1.192 1.193 1.194 1.195 1.196 ?24 ?23 ?22 ?21 ?20 ?19 figure 3. vfbq feedback voltage vs. ambient temperature 0.795 0.797 0.799 0.801 0.803 0.805 0.807 0.809 200 250 300 350 400 450 500 550 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 ?2.5 ?1.5 ?0.5 0.5 1.5 2.5 figure 4. oscillation frequency in s0/s3 vs. ambient temperature figure 5. vfb1p5 feedback voltage vs. ambient temperature figure 6. vtt sink current load regulation vs. ambient temperature figure 7. vtt source current load regulation vs. ambient temperature figure 8. vtt, output voltage vs. load current 0 20406080 t a , ambient temperature ( c) vfbq, feedback voltage (v) 0 20406080 t a , ambient temperature ( c) vfb1p5, feedback voltage (v) 0 20406080 t a , ambient temperature ( c) vtt, source current load regulation (mvp?p) s3 mode s0 mode 2.0 a sinking current with 10 ms period and 1.0 ms pulse width 2.0 a sourcing current with 10 ms period and 1.0 ms pulse width
ncp5220 http://onsemi.com 8 typical operating waveforms channel 1: vddq output voltage, 1.0 v/div channel 2: vtt output voltage, 1.0 v/div channel 3: v1p5 output voltage, 1.0v/div time base: 5.0 ms/div figure 9. power?up sequence 500 ma applied to vddq 417 ma applied to vtt 288 ma applied to v1p5 channel 1: slp_s5 pin voltage, 5.0 v/div channel 2: vddq output voltage, 1.0 v/div channel 3: vtt output voltage, 1.0 v/div channel 4: v1p5 output voltage, 1.0 v/div time base: 10 ms/div channel 1: slp_s3 pin voltage, 5.0 v/div channel 2: vddq output voltage, ac?coupled, 20 mv/div channel 3: vtt output voltage, ac?coupled, 100 mv/div channel 4: v1p5 output voltage, 50 mv/div time base: 10 ms/div figure 10. s0?s3?s0 t ransition figure 11. s0?s5?s0 t ransition channel 1: current sourced out of vtt, 2.0 a/div channel 2: vddq output voltage, ac?coupled, 100 mv/div channel 3: vtt output voltage, ac?coupled, 20 mv/div channel 4: v1p5 output voltage, ac?coupled, 100 mv/div time base: 200 s/div figure 12. vtt source current transient, 0a?2a?0a
ncp5220 http://onsemi.com 9 typical operating waveforms channel 1: current sunk into vtt, 2.0 a/div channel 2: vddq output voltage, ac?coupled, 100 mv/div channel 3: vtt output voltage, ac?coupled, 50 mv/div channel 4: v1p5 vutput voltage, ac?coupled, 100 mv/div time base: 200 s/div figure 13. vtt sink current transient, 0a?2a?0a channel 1: current sourced into vddq, 10 a/div channel 2: vddq output voltage, ac?coupled, 50 mv/div channel 3: vtt output voltage, ac?coupled, 100 mv/div channel 4: v1p5 output voltage, ac?coupled, 100 mv/div time base: 1.0 ms/div channel 1: current sourced into v1p5, 10 a/div channel 2: vddq output voltage, ac?coupled, 100 mv/div channel 3: vtt output voltage, ac?coupled, 100 mv/div v1p5 output voltage, ac?coupled, 100 mv/div time base: 1.0 ms/div figure 14. vddq source current transient, 0a?20a?0a channel 1: current sourced into vddq, 2.0 a/div channel 2: vddq output voltage, ac?coupled, 50 mv/div time base: 200 s/div figure 15. v1p5 source current transient, 0a?12a?0a figure 16. s3 mode without 12vatx, 0a?2a?0a
ncp5220 http://onsemi.com 10 detailed operation descriptions general the ncp5220 3?in?1 pwm dual buck linear ddr power controller contains two high efficiency pwm controllers and an integrated two?quadrant linear regulator. the vddq supply is produced by a pwm switching controller with two external n?ch fets. the vtt termination voltage is an integrated linear regulator with sourcing and sinking current capability which tracks at ? vddq. the mch cor e voltage is created by the secondary switching controller. the inclusion of soft?start, supply undervoltage monitors and thermal shutdown, makes this device a total power solution for the mch and ddr memory system. this device is packaged in a dfn?20. acpi control logic the acpi control logic is powered by the 5vdual supply. it accepts external control at the slp_s3 input and internal supply voltage monitoring signals from two uvlos to decode the operating mode in accordance with the state transition diagram in figure 18. these uvlos monitor the external supplies, 5vdual and 12vatx, through 5vdual and boot pins respectively. two control signals, _5vdualgd and _bootgd, are asserted when the supply voltages are good. when the device is powered up initially, it is in the s5 shutdown mode to minimize the power consumption. when all three supply voltages are good with slp_s3 and slp_s5 remaining high, the device enters the s0 normal operating mode. the transition of slp_s3 from high to low while in the s0 mode, triggers the device into the s3 sleep mode. in s3 mode the 12vatx supply collapses. on transition of slp_s3 from low to high, the device returns to s0 mode. the ic can re?enter s5 mode by setting slp_s5 low. a timing diagram is shown in figure 17. table 1 summarizes the operating states of all the regulators, as well as the conditions of the output pins. internal bandgap voltage reference an internal bandgap reference is generated whenever 5vdual exceeds 2.7 v. once this bandgap reference is in regulation, an internal signal _vrefgd will be asserted. s5 to s0 mode power?up sequence the acpi control logic is enabled by the assertion of _vrefgd. once the acpi control is activated, the power? up sequence starts by waking up the 5vdual voltage monitor block. if the 5vdual supply is within the preset levels, the boot undervoltage monitor block is then enabled. after 12vatx is ready and the boot uvlo is asserted low, the acpi control triggers this device from s5 shutdown mode into s0 normal operating mode by activating the soft?start of ddq switching regulator, providing slp_s3 and slp_s5 remain high. once the ddq regulator is in regulation and the soft?start interval is completed, the _inregddq signal is asserted high to enable the vtt regulator as well as the v1p5 switching regulator. ddq switching regulator in s0 mode the ddq regulator is a switching synchronous rectification buck controller driving two external power n?ch fets to supply up to 20 a. it employs voltage mode fixed frequency pwm control with external compensation switching at 250khz 13.2%. as shown in figure 2, the vddq output voltage is divided down and fed back to the inverting input of an internal amplifier through the fbddq pin to close the loop at vddq = vfbq (1 + r1/r2). this amplifier compares the feedback voltage with an internal reference voltage of 1.190 v to generate an error signal for the pwm comparator. this error signal is compared with a fixed frequency ramp waveform derived from the internal oscillator to generate a pulse?width?modulated signal. this pwm signal drives the external n?ch fets via the tg_ddq and bg_ddq pins. external inductor l and capacitor cout1 filter the output waveform. when the ic leaves the s5 state, the vddq output voltage ramps up at a soft?start rate controlled by the capacitor at the ss pin. when the regulation of vddq is detected in s0 mode, _inregddq goes high to notify the control block. in s3 standby mode, the switching frequency is doubled to reduce the conduction loss in the external n?ch fets. table 1. mode, operation and output pin conditions operating conditions output pin conditions mode ddq vtt mch tg_ddq bg_ddq tp_1p5 bg_1p5 s0 normal normal normal normal normal normal normal s3 standby h?z off standby standby low low s5 off h?z off low low low low
ncp5220 http://onsemi.com 11 for enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a diode or schottky diode rectifier. adaptive non?overlap timing control of the complementary gate drive output signals is provided to reduce shoot?through current that degrades efficiency. tolerance of vddq both the tolerance of vfbq and the ratio of the external resistor divider r1/r2 impact the precision of vddq. with the control loop in regulation, vddq = vfbq (1 + r1/r2). with a worst case (for all valid operating conditions) vfbq tolerance of 1.5%, a worst case range of 2% for vddq will be assured if the ratio r1/r2 is specified as 1.100 1%. fault protection of vddq regulator in s0 mode, an internal voltage (vocp) = 5vdual ? 0.8 sets the current limit for the high?side switch. the voltage vocp pin is compared to the voltage at swddq pin when the high?side gate drive is turned on after a fixed period of blanking time to avoid false current limit triggering. when the voltage at swddq is lower than vocp, an overcurrent condition occurs and all regulators are latched off to protect against overcurrent. the ic will be powered up again if one of the supply voltages, 5vdual, slp_s5 or 12vatx, is recycled. the main purpose is for fault protection, not for precise current limit. in s3 mode, this overcurrent protection feature is disabled. feedback compensation of vddq regulator the compensation network is shown in figure 2. vtt active terminator the vtt active terminator is a 2 quadrant linear regulator with two internal n?ch fets to provide current sink and source capability up to 2.0 a. it is activated only when the ddq regulator is in regulation in s0 mode. it draws power from vddq with the internal gate drive power derived from 5vdual. while vtt output is connecting to the fbvtt pin directly, vtt voltage is designed to automatically track at the half of vddq. this regulator is stable with any value of output capacitor greater than 470 f, and is insensitive to esr ranging from 1 m to 400 m . fault protection of vtt active terminator to provide protection for the internal fet s, bi?directional current limit preset at 2.4 a magnitude is implemented. the vtt provides a soft?start function during start up. mch switching regulator the secondary switching regulator is identical to the ddq regulator except the output is 10 a. no fault protection is implemented and the soft?start timing is twice as fast with respect to css. boot pin supply voltage in typical application, a flying capacitor is connected between swddq and boot pins. in s0 mode, 12vatx is tied to boot pin through a schottky diode as well. a 13 v zener clamp circuit must clamp this boot strapping voltage produced by the flying capacitor in s0 mode. in s3 mode the 12vatx is collapsed and the boot voltage is created by the schottky diode between 5vdual and boot pins as well as the flying capacitor. the boot_uvlo works specially. the _bootgd goes low and the ic remains in s3 mode. thermal consideration assuming an ambient temperature of 50 c, the maximum allowed dissipated power of dfn?20 is 2.8 w, which is enough to handle the internal power dissipation in s0 mode. to take full advantage of the thermal capability of this package, the exposed pad underneath must be soldered directly onto a pcb metal substrate to allow good thermal contact. thermal shutdown when the junction temperature of the ic exceeds 145 c, the entire ic is shutdown. when the junction temperature drops below 120 c, the chip resumes normal operation.
ncp5220 http://onsemi.com 12 5vstby or 5vdual 12 v slp_s5 ss pin ddq?s0 mch state 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 so s3 so s5 11 vtt slp_s3 2. 5vstby or 5vstb is the ultimate chip enable, slp_s5 and slp_s3 go high. this supply has to be up first to ensure gates are in known state. 3. 12 v supply ramp. 4. ddq will ramp with the tracking of ss pin, timing is 1.2 * c ss / 4 (sec). 5. ddq ss is completed, then ss pin is released from ddq. ss pin is shorted to ground. 5. mch ramps with the tracking of ss pin ramp, timing is 0.8 * c ss / 8 (sec). vtt start up with current limit. 6. mch ss is completed, then ss pin is released from mch, ss pin is shorted to ground. s0 mode. 7. s3 mode ?? slp_s3 = l. 8. vtt and mch will be turned off. 9. 12 v ramps to 0 v. 10. standard s3 state. 11. slp_s3 goes high. 12. 12 v ramps back to regulation. 13. 12 v uvlo = l and slp_s3 = h. mch ramps with ss pin, timing is 0.8 * c ss / 8 (sec). vtt rises. 14. s0 mode. 15. s5 mode ?? slp_s5 = l. 16. ddq, vtt and mch turned off. 17. s5 mode. figure 17. ncp5220 power?up and power?down switching frequency doubles
ncp5220 http://onsemi.com 13 s5 s0 s3 slp_s3 = 1 and slp_s5 = 1 and _bootgd = 1 note: 5vdual is assumed to be in good conditions in any mode. all possible state transitions are shown. all unspecified inputs do not cause any state change. figure 18. transitions state diagram of ncp5220 slp_s3 = 1 and slp_s5 = 1 and _bootgd = 1 slp_s3 = 0 and slp_s5 = 1 slp_s5 = 0 or (slp_s3 = 1 and _bootgd = 0) slp_s5 = 0
ncp5220 http://onsemi.com 14 application information application circuit figure 20, on the following page, shows the typical application circuit for ncp5220. the ncp5220 is specifically designed as a total power solution for the mch and ddr memory system. this diagram contains ncp5220 for driving four external n?ch fets to form the ddr memory supply voltage (vddq) and the mch regulator. output inductor selection the value of the output inductor is chosen by balancing ripple current with transient response capability. a value of 1.7 h will yield about 3.0 a peak?peak ripple current when converting from 5.0 v to 2.5 v at 250 khz. it is important that the rated inductor current is not exceeded during full load, and that the saturation current is not less than the expected peak current. low esr inductors may be required to minimize dc losses and temperature rise. input capacitor selection input capacitors for pwm power supplies are required to provide a stable, low impedance source node for the buck regulator to convert from. the usual practice is to use a combination of electrolytic capacitors and multi?layer ceramic capacitors to provide bulk capacitance and high frequency noise suppression. it is important that the capacitors are rated to handle the ac ripple current at the input of the buck regulators, as well as the input voltage. in the ncp5220 the ddq and mch regulators are interleaved (out of phase by 180 degrees) to reduce the peak ac input current. output capacitor selection output capacitors are chosen by balancing the cost with the requirements for low output ripple voltage and transient voltage. low esr electrolytic capacitors can be effective at reducing ripple voltage at 250 khz. low esr ceramic capacitors are most effective at reducing output voltage excursions caused by fast load steps of system memory and the memory controller. power mosfet selection power mosfets are chosen by balancing the cost with the requirements for the current load of the memory system and the efficiency of the converter provided. the selections criteria can be based on drain?source voltage, drain current, on?resistance r ds(on) and input gate capacitance. low r ds(on) and high drain current power mosfets are usually preferred to achieve the high current requirement of the ddr memory system and mch, as well as the high efficiency of the converter. the tradeoff is a corresponding increase in the input gate capacitor of the power mosfets. pcb layout considerations with careful pcb layout the ncp5220 can supply 20 a or more of current. it is very important to use wide traces or large copper shapes to carry current from the input node through the mosfet switches, inductor and to the output filters and load. reducing the length of high current nodes will reduce losses and reduce parasitic inductance. it is usually best to locate the input capacitors the mosfet switches and the output inductor in close proximity to reduce dc losses, parasitic inductance losses and radiated emi. the sensitive voltage feedback and compensation networks should be placed near the ncp5220 and away from the switch nodes and other noisy circuit elements. placing compensation components near each other will minimize the loop area and further reduce noise susceptibility. optional boost voltage configuration the charge pump circuit in figure 19 can be used instead of boost voltage scheme of figure 20. the advantage in figure 19 is the elimination of the requirement for the zener clamp. sw_ddq bg_ddq tg_ddq boot 5vdual comp_1p5 tg_1p5 bg_1p5 gnd_1p5 slp_s3 ncp5220 20 19 18 17 16 15 14 13 12 11 5vdual tp2 r2 4.7 r3 1 k r4 4.7 3 4 1 3 4 1 dpak q2 ntd40n03 d1 bat54ht1 l d2 bat54ht1 c4 100 nf 12vatx tp2 2.5 vddq tp5 c6 4.7 f c7 2200 f + + c25 2200 f vddq r15 1 k figure 19. charge pump circuit at boot pin d2 bat54ht1 5vdual q2 ntd40n03
ncp5220 http://onsemi.com 15 vddq r5 2.2 k r6 8 c9 100 nf c8 10 nf c10 6.8 nf r7 20 k r8 2 k sgnd 1 2 3 4 5 6 7 8 9 10 + c1 33 sgnd tp7 1.25 vtt vtt r16 1 k c12 4.7 f c13 470 f c24 470 f + + r18 51 k vddq c20 470 f sgnd sgnd u1 vref = 1.20 v comp fbddq ss pgnd vtt vddq agnd fbvtt slp_s5 fb1p5 sw_ddq bg_ddq tg_ddq boot 5vdual comp_1p5 tg_1p5 bg_1p5 gnd_1p5 slp_s3 ncp5220 20 19 18 17 16 15 14 13 12 11 5vdual tp2 5vdual l1 1 f + c2 3300 f r13 2.2 k r6 8 c18 100 nf c16 10 nf c17 6.8 nf r12 20 k filtered 5vdual c23 10 f + c11 c21 100 f 220 nf nf r2 2.2 r3 1 k r4 1 3 4 1 3 4 1 dpak q2 85n02r dpak q1 85n02r c4 22 nf d1 bat54ht1 l2 1.8 h d2 bat54ht1 zener mmsz13t1 c5 470 f 12vatx tp2 2.5 vddq tp5 c6 4.7 f c7 2200 f + + c25 2200 f r9 4.7 r10 4.7 3 4 1 3 4 1 dpak q5 dpak q4 40n03r 40n03r c22 10 f c3 3300 f + filtered 5vdual l3 1.8 h agnd to pgnd vddq comp_1p5 vref = 800 mv r14 2 k r15 1 k c14 4.7 f c26 2200 f + + c15 2200 f vcmh r17 1 k 1.5 vmch tp8 agnd to pgnd gnd tp16 sgnd figure 20. ncp5220 typical application circuit 5vdual
ncp5220 http://onsemi.com 16 table 2. bill of material of ncp5220 application circuit reference design description value qty part number manufactur q1, q2 power mosfet n?channel 24 v, 4.8 m , 85 a 2 ntd85n02r on semiconductor q3, q4 power mosfet n?channel 25 v, 12.6 m , 40 a 2 ntd40n03r on semiconductor d1, d2 rectifier schottky diode 30 v 2 bat54ht1 on semiconductor u1 controller 3?in?1 pwm dual buck and linear power controller 1 ncp5220 on semiconductor zener zener diode 13 v, 0.5 w 1 mmsz13t1 on semiconductor l1 toroidal choke 1.0 h, 25 a 1 t60?26(6t) l2, l3 toroidal choke 1.8 h, 25 a 2 t50?26b(6t) c2, c3 aluminum electrolytic capacitor 3300 f, 6.3 v 2 eeufj0j332u panasonic c5 aluminum electrolytic capacitor 470 f, 35 v 1 eeufc1v471 panasonic c21 aluminum electrolytic capacitor 100 f, 50 v 1 eeufc1h101 panasonic c20 aluminum electrolytic capacitor 470 f, 16 v 1 eeufc1c471 panasonic c13, c24 aluminum electrolytic capacitor 470 f, 10 v 2 eeufc1a471 panasonic c7, c25, c15, c26 aluminum electrolytic capacitor 2200 f, 6.3 v 4 eeufc0j222s(h) panasonic c11 ceramic capacitor 220 nf, 10 v 1 ecj1vb1a224k panasonic c6, c12, c14 ceramic capacitor 4.7 f, 6.3 v 3 ecjhvb0j475m panasonic c22, c23 ceramic capacitor 10 f, 25 v 2 ecj4yb1e106m panasonic c4 ceramic capacitor 22 nf, 25 v 1 ecj1vb1e223k panasonic c10, c17 ceramic capacitor 6.8 nf, 50 v 2 ecj1vb1h682k panasonic c9, c18 ceramic capacitor 100 nf, 16 v 2 ecj1vb1c104k panasonic c8, c16 ceramic capacitor 10 nf, 50 v 2 ecj1vb1h103k panasonic c1 ceramic capacitor 33 nf, 25 v 1 ecj1vb1e333k panasonic r2 resistor 2.2 1 r4 resistor 1.0 1 r9, r10 resistor 4.7 2 r3, r15, r16, r17 resistor 1.0 k 4 r7, r12 resistor 20 k 2 r6, r13 resistor 8.2 2 r8, r14 resistor 2.0 k 2 r5, r11 resistor 2.2 k 2 r18 resistor 51 k 1
ncp5220 http://onsemi.com 17 package dimensions 20 pin dfn, dual?sided, 5x6 mm mn suffix case 505ab?01 issue a c 0.15 e2 d2 l b 20x a d notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b applies to plated terminals and is measured between 0.25 and 0.30 mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. e c e a b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a2 0.65 0.75 a3 0.20 ref b 0.23 0.28 d 6.00 bsc d2 3.98 4.28 e 5.00 bsc e2 2.98 3.28 e 0.50 bsc k 0.20 ??? l 0.50 0.60 c 0.15 pin 1 location a1 (a3) seating plane c 0.08 c 0.10 a2 20x k 20x a 0.10 b c 0.05 c note 3 110 11 20 2x 2x top view side view bottom view
ncp5220 http://onsemi.com 18 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp5220/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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